1. Field of the Invention
This invention relates to a charge imaging matrix (CIM) and, more specifically, to a charge imaging matrix utilizing only two gate levels.
2. Description of the Prior Art
Charge imaging matrix devices as produced in the prior art generally have three different gate levels. A gate level is defined herein as a semiconductor with insulator on a surface thereof in a layer and an electrically conductive gate level thereon followed by a further insulator layer. For three levels to exist a further gate level and a further insulator level and still a further gate level are provided, each gate level being separately deposited and electrically isolated from the remaining gate levels. Each metal level is a separate gate level and is separated from the adjacent gates by insulator as stated above. In accordance with the definition of a gate level as is used herein, a gate which is positioned at two different physical levels but deposited at one time is considered to be a single gate level.
A charge imaging matrix comprises three essential components, one being a detector gate which collects or senses charge that comes in and collects thereunder, the second being a diode and the third being a transfer gate between the detector gate and the diode which allows one to transfer charge which has been collected under the detector gate into the diode. This arrangement has required the three gate levels in the prior art as described above, one for the detector gate, one for the transfer gate and one for a field plate which solves a problem having to do with the surface of the HgCdTe semiconductor substrate.
In the currently used designs for a CIM cell utilizing the above described structure having three gate levels, all electrically independent, optically generated charge is collected under the detector gate. A surface channel is created under the transfer gate by biasing it to a weak inversion level. The well under the detector gate is collapsed, forcing the charge through the surface channel to the diode where it is sensed and drained. The transfer gate may be turned on only when charge transfer is desired. Alternatively, the transfer gate may be left on at all times if the well created thereunder is small compared to the size (depth into the material) of the well under the detector gate. The third gate in the structure is used simply for maintaining the rest of the surface of the semiconductor substrate at flat band and preventing unwanted surface channels.
The problem is that there is a fixed positive charge in the insulator which converts the surface of the semiconductor thereunder to a depletion area and causes a surface channel to exist. This requires the fabrication of the three gate levels as described. In the manufacture of charge image matrix devices of the prior art, the three gates have been positioned relative to the semiconductor material such that the field plate was closest thereto followed by the detector gate and then the transfer gate. Since the gate levels must be separated by an insulator level, it is apparent that the detector gate is not as close to the semiconductor surface as would be desirable since it is known that the farther the detector gate is from the semiconductor surface, the less charge storage capacity is available thereunder. It is also readily apparent that, with an increase in processing steps, the product yield must invariably suffer.